diff options
author | Hannah Williams <hannah.williams@intel.com> | 2017-05-05 16:30:22 -0700 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-21 03:59:09 +0000 |
commit | 3ff14a0c8590705ba4cc184f6e9d6e5f6302fb4c (patch) | |
tree | b7e9a0d1a14365ff1cdccce168dc6c94d0e05e0d /src/soc/intel/apollolake/Makefile.inc | |
parent | a77c68adf3a566e3eaa676d5fa4080ed41199e4b (diff) |
soc/intel/apollolake: Bring in delta for GLK SOC
Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/Makefile.inc')
-rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index bf445e5628..af4efc191b 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -9,9 +9,7 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/bootblock.c bootblock-y += car.c -bootblock-y += gpio_apl.c bootblock-y += heci.c bootblock-y += i2c.c bootblock-y += lpc_lib.c @@ -23,7 +21,6 @@ bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c -romstage-y += gpio_apl.c romstage-y += heci.c romstage-y += i2c.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c @@ -37,7 +34,6 @@ romstage-y += spi.c smm-y += mmap_boot.c smm-y += pmutil.c -smm-y += gpio_apl.c smm-y += smihandler.c smm-y += spi.c smm-y += uart_early.c @@ -48,7 +44,6 @@ ramstage-y += chip.c ramstage-y += cse.c ramstage-y += elog.c ramstage-y += dsp.c -ramstage-y += gpio_apl.c ramstage-y += graphics.c ramstage-y += heci.c ramstage-y += i2c.c @@ -87,8 +82,24 @@ verstage-y += pmutil.c verstage-y += reset.c verstage-y += spi.c +ifeq ($(CONFIG_SOC_INTEL_GLK),y) +bootblock-y += gpio_glk.c +romstage-y += gpio_glk.c +smm-y += gpio_glk.c +ramstage-y += gpio_glk.c +else +bootblock-y += gpio_apl.c +romstage-y += gpio_apl.c +smm-y += gpio_apl.c +ramstage-y += gpio_apl.c +endif + CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include +ifeq ($(CONFIG_SOC_INTEL_GLK),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk +else CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/apollolake +endif # Since FSP-M runs in CAR we need to relocate it to a specific address $(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) |