soc/intel/apollolake: Add basic HECI support

Add functions to read Host Firmware Status register and a helper
function to determine if CSE is ready.

BUG=chrome-os-partner:55055
TEST=none

Change-Id: If511a51c04f7e59427d7952fa67b61060e2be404
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15713
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 4 insertions, 0 deletions

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index c44fc464d5..fda3523454 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -13,6 +13,7 @@ bootblock-y += bootblock/cache_as_ram.S
 bootblock-y += bootblock/bootblock.c
 bootblock-y += car.c
 bootblock-y += gpio.c
+bootblock-y += heci.c
 bootblock-y += itss.c
 bootblock-y += lpc_lib.c
 bootblock-y += mmap_boot.c
@@ -24,6 +25,7 @@ bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 romstage-y += car.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
 romstage-y += gpio.c
+romstage-y += heci.c
 romstage-y += i2c_early.c
 romstage-y += itss.c
 romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
@@ -49,6 +51,7 @@ ramstage-y += chip.c
 ramstage-y += dsp.c
 ramstage-y += gpio.c
 ramstage-y += graphics.c
+ramstage-y += heci.c
 ramstage-y += i2c.c
 ramstage-y += itss.c
 ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
@@ -77,6 +80,7 @@ postcar-y += tsc_freq.c
 
 verstage-y += car.c
 verstage-y += i2c_early.c
+verstage-y += heci.c
 verstage-y += memmap.c
 verstage-y += mmap_boot.c
 verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c