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authorSubrata Banik <subrata.banik@intel.com>2017-03-03 18:23:59 +0530
committerMartin Roth <martinroth@google.com>2017-03-28 16:39:01 +0200
commitfc4c7d8320d329d3712cb74e527dca4178f71bf8 (patch)
tree41bfe5e1b64cbf070a378309e49df5be3cd3f881 /src/soc/intel/apollolake/Makefile.inc
parent03e971cd23e96b9293fc3ecc420f56ad91326cd9 (diff)
soc/intel/apollolake: Clean up code by using common CAR init
This patch currently contains common CAR initialization required in bootblock phase along with common MSR header - 1. Use SOC_INTEL_COMMON_BLOCK_CAR to have common CAR initialization and CAR teardown. 2. Use common MSR header "intelblocks/msr.h" inside soc/cpu.h Change-Id: I67f909f50a24f009b3e35388665251be1dde40f7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18555 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/Makefile.inc')
-rw-r--r--src/soc/intel/apollolake/Makefile.inc13
1 files changed, 2 insertions, 11 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 411bf585b4..1e6aafdbcd 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -21,12 +21,7 @@ bootblock-y += pmutil.c
bootblock-y += spi.c
bootblock-y += tsc_freq.c
bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
-
-ifeq ($(CONFIG_FSP_CAR),y)
-bootblock-y += bootblock/cache_as_ram_fsp.S
-else
-bootblock-y += bootblock/cache_as_ram.S
-endif
+bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
romstage-y += car.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
@@ -94,11 +89,7 @@ postcar-y += spi.c
postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
postcar-y += tsc_freq.c
-ifeq ($(CONFIG_FSP_CAR),y)
-postcar-y += exit_car_fsp.S
-else
-postcar-y += exit_car.S
-endif
+postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
verstage-y += car.c
verstage-y += flash_ctrlr.c