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authorFurquan Shaikh <furquan@chromium.org>2017-08-05 11:12:44 -0700
committerFurquan Shaikh <furquan@google.com>2017-08-10 16:25:14 +0000
commitea4ece61b6fc787c652a193ecd04c075daca3158 (patch)
tree44ce6dc1af1cd2f7ef61bd4510e3da694fd9119d /src/soc/intel/apollolake/Makefile.inc
parent96024836077d28100035950e517b2ae5ad1ab5d9 (diff)
soc/intel/apollolake: Enable UART debug controller on S3 resume
1. Add a new variable to GNVS to store information during S3 suspend whether UART debug controller is enabled. 2. On resume, read stored GNVS variable to decide if UART debug port controller needs to be initialized. 3. Provide helper functions required by intel/common UARRT driver for enabling controller on S3 resume. BUG=b:64030366 Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20888 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/Makefile.inc')
-rw-r--r--src/soc/intel/apollolake/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 07bbdcdc65..589b846012 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -42,6 +42,7 @@ smm-y += pmutil.c
smm-y += smihandler.c
smm-y += spi.c
smm-y += uart_early.c
+smm-y += uart.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-y += cpu.c