diff options
| author | Brenton Dong <brenton.m.dong@intel.com> | 2016-10-18 13:57:54 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-21 00:11:24 +0100 |
| commit | c9b398191e5f94647b3e4e80bafb5331ae49b7c8 (patch) | |
| tree | 83c28799810ff66585bd26a9f21a0aaff6afa07e /src/soc/intel/apollolake/Makefile.inc | |
| parent | 0a5971c91bac57970e3f3229b8cda735a17b3a67 (diff) | |
soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize
& tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to
ApolloLake SoC when CONFIG_FSP_CAR is enabled.
Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.
Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17063
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index d058ddbbba..5a65f43485 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c bootblock-y += flash_ctrlr.c @@ -23,6 +22,12 @@ bootblock-y += spi.c bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +ifeq ($(CONFIG_FSP_CAR),y) +bootblock-y += bootblock/cache_as_ram_fsp.S +else +bootblock-y += bootblock/cache_as_ram.S +endif + romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += flash_ctrlr.c @@ -79,7 +84,6 @@ ramstage-y += sram.c ramstage-y += spi.c ramstage-y += xhci.c -postcar-y += exit_car.S postcar-y += flash_ctrlr.c postcar-y += memmap.c postcar-y += mmap_boot.c @@ -87,6 +91,12 @@ postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c +ifeq ($(CONFIG_FSP_CAR),y) +postcar-y += exit_car_fsp.S +else +postcar-y += exit_car.S +endif + verstage-y += car.c verstage-y += flash_ctrlr.c verstage-y += i2c_early.c |