soc/intel/apollolake: Clean up UART code

Clean up and move UART related code under a single uart.c file.

Change-Id: I9a30258ba43ee5920f585c1bd06bc25773778ec4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

1 files changed, 6 insertions, 8 deletions

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 60f4ee37a9..68f294743b 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -16,14 +16,14 @@ bootblock-y += lpc.c
 bootblock-y += mmap_boot.c
 bootblock-y += pmutil.c
 bootblock-y += spi.c
-bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+bootblock-$(CONFIG_SOC_UART_DEBUG) += uart.c
 bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
 
 romstage-y += car.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
 romstage-y += heci.c
 romstage-y += i2c.c
-romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+romstage-$(CONFIG_SOC_UART_DEBUG) += uart.c
 romstage-y += memmap.c
 romstage-y += meminit.c
 ifeq ($(CONFIG_SOC_INTEL_GLK),y)
@@ -40,8 +40,7 @@ smm-y += mmap_boot.c
 smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += spi.c
-smm-y += uart_early.c
-smm-y += uart.c
+smm-$(CONFIG_SOC_UART_DEBUG) += uart.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += cpu.c
@@ -51,11 +50,10 @@ ramstage-y += elog.c
 ramstage-y += graphics.c
 ramstage-y += heci.c
 ramstage-y += i2c.c
-ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 ramstage-y += lpc.c
 ramstage-y += memmap.c
 ramstage-y += mmap_boot.c
-ramstage-y += uart.c
+ramstage-$(CONFIG_SOC_UART_DEBUG) += uart.c
 ramstage-y += nhlt.c
 ramstage-y += spi.c
 ramstage-y += systemagent.c
@@ -69,7 +67,7 @@ ramstage-y += sd.c
 postcar-y += memmap.c
 postcar-y += mmap_boot.c
 postcar-y += spi.c
-postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+postcar-$(CONFIG_SOC_UART_DEBUG) += uart.c
 
 postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
 
@@ -78,7 +76,7 @@ verstage-y += i2c.c
 verstage-y += heci.c
 verstage-y += memmap.c
 verstage-y += mmap_boot.c
-verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+verstage-$(CONFIG_SOC_UART_DEBUG) += uart.c
 verstage-y += pmutil.c
 verstage-y += reset.c
 verstage-y += spi.c