soc/intel: Clean mess around UART_DEBUG

Everything is wrong here, the Kconfig symbols are only the tip of the
iceberg. Based on Kconfig prompts the SoC code performed pad configu-
rations! I don't see why the person who configures coreboot should have
the board schematics at hand.

As a mitigation, we remove the prompts for UART_DEBUG, which is renamed
to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say
what it's about), and for UART_FOR_CONSOLE in case the former is selec-
ted.

Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 6 insertions, 6 deletions

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 19ebe7c55b..822158c3c1 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -18,14 +18,14 @@ bootblock-y += lpc.c
 bootblock-y += mmap_boot.c
 bootblock-y += pmutil.c
 bootblock-y += spi.c
-bootblock-$(CONFIG_UART_DEBUG) += uart.c
+bootblock-y += uart.c
 
 romstage-y += car.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
 romstage-y += gspi.c
 romstage-y += heci.c
 romstage-y += i2c.c
-romstage-$(CONFIG_UART_DEBUG) += uart.c
+romstage-y += uart.c
 romstage-y += memmap.c
 romstage-y += meminit.c
 ifeq ($(CONFIG_SOC_INTEL_GLK),y)
@@ -42,7 +42,7 @@ smm-y += mmap_boot.c
 smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += spi.c
-smm-$(CONFIG_UART_DEBUG) += uart.c
+smm-y += uart.c
 smm-y += elog.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
@@ -57,7 +57,7 @@ ramstage-y += i2c.c
 ramstage-y += lpc.c
 ramstage-y += memmap.c
 ramstage-y += mmap_boot.c
-ramstage-$(CONFIG_UART_DEBUG) += uart.c
+ramstage-y += uart.c
 ramstage-y += nhlt.c
 ramstage-y += spi.c
 ramstage-y += systemagent.c
@@ -74,7 +74,7 @@ postcar-y += spi.c
 postcar-y += i2c.c
 postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c
 postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c
-postcar-$(CONFIG_UART_DEBUG) += uart.c
+postcar-y += uart.c
 postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c
 
 verstage-y += car.c
@@ -83,7 +83,7 @@ verstage-y += gspi.c
 verstage-y += heci.c
 verstage-y += memmap.c
 verstage-y += mmap_boot.c
-verstage-$(CONFIG_UART_DEBUG) += uart.c
+verstage-y += uart.c
 verstage-y += pmutil.c
 verstage-y += reset.c
 verstage-y += spi.c