diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2016-03-04 21:33:04 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-03-10 22:57:00 +0100 |
| commit | 9d903a1dd352ce16c6e6feee5f63e3b21c821111 (patch) | |
| tree | ad205ae29d6874a3ca5619ce6e7493c598b5dcb6 /src/soc/intel/apollolake/Makefile.inc | |
| parent | 7760261db770aeee520aac2c313af764b606d4bf (diff) | |
soc/apollolake: Enable all CPU cores using the parallel MP lib
This is the minimal setup needed to get all CPU cores enabled. That
includes sending an IPI to APs and setting up MTRRs. Microcode updates
are not performed for two reasons:
* CSE (Converged Security Engine) upgrades the microcode before
releasing reset
* Microcode update files are not available at this point in time
Change-Id: Ia1115983696b0906fb4cefcbe1bbe4fc100751ca
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index dd2213e869..3b31f12c6b 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -6,6 +6,7 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S @@ -24,6 +25,7 @@ romstage-y += memmap.c romstage-y += mmap_boot.c smm-y += placeholders.c +ramstage-y += cpu.c ramstage-y += placeholders.c ramstage-y += gpio.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c |