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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-05-23 18:17:14 +0530
committerAaron Durbin <adurbin@chromium.org>2017-06-09 20:01:26 +0200
commit66fe0c43be7d886bec8c8aef55c406a53e65642e (patch)
treee220be03cbba401f8ad1ceed61d20c4a22a2f906 /src/soc/intel/apollolake/Makefile.inc
parent1517bab69303dba1166a2f78b84f647618bbd003 (diff)
soc/intel/apollolake: Use CPU common library code
This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I529c67cf20253cf819d1c13849300788104b083c Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19827 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/Makefile.inc')
-rw-r--r--src/soc/intel/apollolake/Makefile.inc6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index b1f92f04d0..619713876e 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -18,7 +18,6 @@ bootblock-y += lpc_lib.c
bootblock-y += mmap_boot.c
bootblock-y += pmutil.c
bootblock-y += spi.c
-bootblock-y += tsc_freq.c
bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
@@ -32,7 +31,6 @@ romstage-y += lpc_lib.c
romstage-y += memmap.c
romstage-y += meminit.c
romstage-y += mmap_boot.c
-romstage-y += tsc_freq.c
romstage-y += pmutil.c
romstage-y += reset.c
romstage-y += spi.c
@@ -42,7 +40,6 @@ smm-y += pmutil.c
smm-y += gpio.c
smm-y += smihandler.c
smm-y += spi.c
-smm-y += tsc_freq.c
smm-y += uart_early.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
@@ -65,7 +62,6 @@ ramstage-y += uart.c
ramstage-y += nhlt.c
ramstage-y += systemagent.c
ramstage-y += spi.c
-ramstage-y += tsc_freq.c
ramstage-y += pmutil.c
ramstage-y += pmc.c
ramstage-y += reset.c
@@ -79,7 +75,6 @@ postcar-y += memmap.c
postcar-y += mmap_boot.c
postcar-y += spi.c
postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
-postcar-y += tsc_freq.c
postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
@@ -89,7 +84,6 @@ verstage-y += heci.c
verstage-y += memmap.c
verstage-y += mmap_boot.c
verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
-verstage-y += tsc_freq.c
verstage-y += pmutil.c
verstage-y += reset.c
verstage-y += spi.c