soc/intel/apollolake: Add support for memory-mapped boot media

On Apollo Lake SPI flash is memory mapped. The mapping is different
to previous platforms. Only "BIOS" region is mapped in contrast to
whole flash. Also, the 128 KiB right below 4 GiB are being decoded by
readonly SRAM. Fail accesses to those regions, rather than returning
false data.

Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13706
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 3 insertions, 0 deletions

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 76fa4c7050..e27fd27128 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -11,6 +11,7 @@ bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/cache_as_ram.S
 bootblock-y += bootblock/bootblock.c
 bootblock-y += gpio.c
+bootblock-y += mmap_boot.c
 bootblock-y += placeholders.c
 bootblock-y += tsc_freq.c
 bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
@@ -18,11 +19,13 @@ bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 romstage-y += placeholders.c
 romstage-y += gpio.c
 romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+romstage-y += mmap_boot.c
 
 smm-y += placeholders.c
 ramstage-y += placeholders.c
 ramstage-y += gpio.c
 ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+ramstage-y += mmap_boot.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include