soc/intel/apollolake: Add support for GSPI

BUG=b:73133848
BRANCH=None
TEST=Build coreboot for Octopus board. Tested the GSPI interface
with a SPI EEPROM and got correct response to a RDID command

Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/24906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 68f294743b..65df55900d 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -11,6 +11,7 @@ subdirs-y += ../../../cpu/x86/cache
 bootblock-y += bootblock/bootblock.c
 bootblock-y += car.c
 bootblock-y += heci.c
+bootblock-y += gspi.c
 bootblock-y += i2c.c
 bootblock-y += lpc.c
 bootblock-y += mmap_boot.c
@@ -21,6 +22,7 @@ bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
 
 romstage-y += car.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
+romstage-y += gspi.c
 romstage-y += heci.c
 romstage-y += i2c.c
 romstage-$(CONFIG_SOC_UART_DEBUG) += uart.c
@@ -48,6 +50,7 @@ ramstage-y += chip.c
 ramstage-y += cse.c
 ramstage-y += elog.c
 ramstage-y += graphics.c
+ramstage-y += gspi.c
 ramstage-y += heci.c
 ramstage-y += i2c.c
 ramstage-y += lpc.c
@@ -73,6 +76,7 @@ postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
 
 verstage-y += car.c
 verstage-y += i2c.c
+verstage-y += gspi.c
 verstage-y += heci.c
 verstage-y += memmap.c
 verstage-y += mmap_boot.c