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authorFurquan Shaikh <furquan@google.com>2016-06-19 23:20:43 -0700
committerFurquan Shaikh <furquan@google.com>2016-06-21 20:39:32 +0200
commit0be3da53c6eb1b4c05a51151c8059fbb4d4024ac (patch)
treedf28800d0efd5421a503101adefb658797b888d7 /src/soc/intel/apollolake/Makefile.inc
parentbdcda710a7e4bc439408eedaf3e66145c6831c90 (diff)
intel/apollolake: Calculate BIOS mmap at runtime
Instead of hard-coding the BIOS region start and end addresses, read BIOS_BFPREG to determine the base and limit for the mapped BIOS region. BUG=chrome-os-partner:54563 Change-Id: Iddd3d4cc945f09e8f147e293bb9144471a6a220d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15269 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/Makefile.inc')
-rw-r--r--src/soc/intel/apollolake/Makefile.inc3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index a7596e43fe..7d49b066fe 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -56,11 +56,13 @@ ramstage-y += tsc_freq.c
ramstage-y += pmutil.c
ramstage-y += pmc.c
ramstage-y += smi.c
+ramstage-y += spi.c
ramstage-y += reset.c
postcar-y += exit_car.S
postcar-y += memmap.c
postcar-y += mmap_boot.c
+postcar-y += spi.c
postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
postcar-y += tsc_freq.c
@@ -71,6 +73,7 @@ verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
verstage-y += tsc_freq.c
verstage-y += pmutil.c
verstage-y += reset.c
+verstage-y += spi.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include