soc/intel/apollolake: Use common gpio for apollolake

No regression observed on a APL platform

Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 4 insertions, 4 deletions

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index fe55ae9b5e..bf445e5628 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -11,7 +11,7 @@ subdirs-y += ../../../cpu/x86/cache
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/bootblock.c
 bootblock-y += car.c
-bootblock-y += gpio.c
+bootblock-y += gpio_apl.c
 bootblock-y += heci.c
 bootblock-y += i2c.c
 bootblock-y += lpc_lib.c
@@ -23,7 +23,7 @@ bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
 
 romstage-y += car.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
-romstage-y += gpio.c
+romstage-y += gpio_apl.c
 romstage-y += heci.c
 romstage-y += i2c.c
 romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
@@ -37,7 +37,7 @@ romstage-y += spi.c
 
 smm-y += mmap_boot.c
 smm-y += pmutil.c
-smm-y += gpio.c
+smm-y += gpio_apl.c
 smm-y += smihandler.c
 smm-y += spi.c
 smm-y += uart_early.c
@@ -48,7 +48,7 @@ ramstage-y += chip.c
 ramstage-y += cse.c
 ramstage-y += elog.c
 ramstage-y += dsp.c
-ramstage-y += gpio.c
+ramstage-y += gpio_apl.c
 ramstage-y += graphics.c
 ramstage-y += heci.c
 ramstage-y += i2c.c