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authorBrandon Breitenstein <brandon.breitenstein@intel.com>2016-09-30 13:57:12 -0700
committerMartin Roth <martinroth@google.com>2016-10-07 18:18:14 +0200
commit135eae91d57354bc1bfae04056e539d3ce1f7f9c (patch)
tree52b9a2d429ac437f570c08e9b3c078a460f90e83 /src/soc/intel/apollolake/Kconfig
parent9344bde4fedfa7caed35aaa45d25c7184edcf4ae (diff)
soc/intel/apollolake: Implement stage cache to improve resume time
This patch enables stage cache to save ~40ms during S3 resume. It saves ramstage in the stage cache and restores it on resume so that ramstage does not have to reinitialize during the resume flow. Stage cache functionality is added to postcar stage since ramstage is called from postcar. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for Reef and tested ramstage being cached Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16833 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/apollolake/Kconfig')
-rw-r--r--src/soc/intel/apollolake/Kconfig6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 3a23dbd0d2..6c178c31d4 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_NHLT
# Misc options
select C_ENVIRONMENT_BOOTBLOCK
+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
select COLLECT_TIMESTAMPS
select COMMON_FADT
select GENERIC_GPIO_LIB
@@ -34,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select NO_FIXED_XIP_ROM_SIZE
- select NO_STAGE_CACHE
select NO_XIP_EARLY_STAGES
select PARALLEL_MP
select PCIEXP_ASPM
@@ -254,4 +254,8 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS
bool
default n
+config SMM_RESERVED_SIZE
+ hex
+ default 0x100000
+
endif