diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-06-27 10:57:13 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2016-07-02 01:18:22 +0200 |
| commit | ff8bce0a5f53652d4d26cb501159e8711f79eb9b (patch) | |
| tree | a66528533f3f26c959f7a2eed1b7c1d707900af4 /src/soc/intel/apollolake/Kconfig | |
| parent | 02fcc887829bc0bf4e98f591de2a199d6a69f2ba (diff) | |
soc/intel/apollolake: Add support for LPSS I2C driver
Support the I2C interfaces on this SOC using the Intel common lpss_i2c
driver. The controllers are supported in pre-ram environments by
setting a temporary base address in bootblock and in ramstage using
the naturally enumerated base address.
The base speed of this controller is 133MHz and the SCL/SDA timing
values that are reported to the OS are calculated using that clock.
This was tested on a google/reef board doing I2C transactions to the
trackpad both in verstage and in ramstage.
Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15480
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/Kconfig')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 8e33015afd..cce06ebbfe 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -41,8 +41,9 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select SMM_TSEG select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_ACPI + select SOC_INTEL_COMMON_LPSS_I2C + select SOC_INTEL_COMMON_SMI select SPI_FLASH select UDELAY_TSC select TSC_CONSTANT_RATE @@ -96,6 +97,11 @@ config CPU_ADDR_BITS int default 36 +config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ + depends on SOC_INTEL_COMMON_LPSS_I2C + int + default 133 + config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL hex "MMIO base address for UART" |