diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2018-11-21 12:36:21 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-23 11:28:19 +0000 |
| commit | 26361862bdff9bc12c31e4f153e83422e21179b6 (patch) | |
| tree | 17807067cfe286cc0df4e15de6baecf2fc54d2d1 /src/soc/intel/apollolake/Kconfig | |
| parent | 52c58929fd8d9011e7990c042418624b567ffa1b (diff) | |
soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratio
Add a Kconfig switch to be able to set the CPU clock to the lowest
possible ratio. If enabled the CPU will consume as little power as
possible while providing the lowest performance.
This setting can be overruled by the OS if it has an p-state driver
which can adjust the clock to its need.
Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/apollolake/Kconfig')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0c0fca9475..c9b17b047d 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -370,12 +370,24 @@ config CPU_BCLK_MHZ config APL_SKIP_SET_POWER_LIMITS bool + depends on !APL_SET_MIN_CLOCK_RATIO default n help Some Apollo Lake mainboards do not need the Running Average Power Limits (RAPL) algorithm for a constant power management. Set this config option to skip the RAPL configuration. +config APL_SET_MIN_CLOCK_RATIO + bool + depends on !APL_SKIP_SET_POWER_LIMITS + default n + help + If the power budget of the mainboard is limited, it can be useful to + limit the CPU power dissipation at the cost of performance by setting + the lowest possible CPU clock. Enable this option if you need smallest + possible CPU clock. This setting can be overruled by the OS if it has an + p-state driver which can adjust the clock to its need. + # M and N divisor values for clock frequency configuration. # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |