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authorKarthikeyan Ramasubramanian <kramasub@google.com>2024-10-30 10:16:11 -0600
committerSubrata Banik <subratabanik@google.com>2024-11-03 06:45:02 +0000
commitcb11ad06c205ce33477204ef56de177ef9277432 (patch)
tree0266e40dc726ca43b687a4a6cfd4cde7acc932fa /src/soc/intel/alderlake
parent214e9743f8476b14f2b59ec51a790f88289874e6 (diff)
soc/intel/alderlake: Do lazy reset after disabling UFS
If the mainboard expects upcoming reset, then skip the reset after disabling UFS. This will reduce the number of resets during firmware update. BUG=b:375444631 TEST=Build Brox BIOS image and boot to OS. Perform a firmware update and confirm that the number of reset is reduced by 2 resets. Change-Id: I4399555302ec23a76f89f406f437f311eea0ef99 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84935 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/soc/intel/alderlake')
-rw-r--r--src/soc/intel/alderlake/include/soc/romstage.h11
-rw-r--r--src/soc/intel/alderlake/romstage/romstage.c7
2 files changed, 17 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h
index 679d538b2d..574c9b7ae1 100644
--- a/src/soc/intel/alderlake/include/soc/romstage.h
+++ b/src/soc/intel/alderlake/include/soc/romstage.h
@@ -20,4 +20,15 @@ enum board_type {
BOARD_TYPE_SERVER = 8
};
+/*
+ * Default implementation indicates that the mainboard does not expect another reset.
+ * Mainboards can override the default implementation to indicate whether they expect
+ * another reset eg. FW Sync for another component on the mainboard. Some silicon init
+ * code eg. disabling UFS, can use this hint to suppress any redundant resets that they
+ * trigger. If the mainboard does not expect another reset, then the silicon init code
+ * can trigger their required reset.
+ *
+ * Return: true when the mainboard expects another reset, false otherwise.
+ */
+bool mainboard_expects_another_reset(void);
#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index ff600db7b0..2f50cd29dd 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -32,6 +32,11 @@
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
+bool __weak mainboard_expects_another_reset(void)
+{
+ return false;
+}
+
static void disable_ufs(void)
{
/* disable USF0 */
@@ -185,7 +190,7 @@ void mainboard_romstage_entry(void)
(CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) {
printk(BIOS_INFO, "Disabling UFS controllers\n");
disable_ufs();
- if (ps->prev_sleep_state == ACPI_S5) {
+ if (ps->prev_sleep_state == ACPI_S5 && !mainboard_expects_another_reset()) {
printk(BIOS_INFO, "Warm Reset after disabling UFS controllers\n");
system_reset();
}