diff options
| author | Lean Sheng Tan <sheng.tan@9elements.com> | 2022-04-01 12:03:51 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2022-04-04 17:48:56 +0000 |
| commit | 9e78dd13577b577f96699710fefd965acda686e1 (patch) | |
| tree | 9e6f2bb50eda7d698ba9ca14e5971537885d197e /src/soc/intel/alderlake | |
| parent | 74d6efc924326b5858fabbafa58ce095d4cca38d (diff) | |
soc/intel/alderlake: Update CPU IDs with correct steppings
Update ADL CPU IDs per correct steppings listed in Intel Doc 626774.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/alderlake')
4 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/intel/alderlake/bootblock/pmc_descriptor.c b/src/soc/intel/alderlake/bootblock/pmc_descriptor.c index c585f70c37..14a9dcb90e 100644 --- a/src/soc/intel/alderlake/bootblock/pmc_descriptor.c +++ b/src/soc/intel/alderlake/bootblock/pmc_descriptor.c @@ -45,7 +45,7 @@ void configure_pmc_descriptor(void) uint8_t si_desc_buf[CONFIG_SI_DESC_REGION_SZ]; struct region_device desc_rdev; - if (cpu_get_cpuid() != CPUID_ALDERLAKE_A0) + if (cpu_get_cpuid() != CPUID_ALDERLAKE_J0) return; if (fmap_locate_area_as_rdev_rw(CONFIG_SI_DESC_REGION, &desc_rdev) < 0) { diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 3342e4b732..721355c06a 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -23,10 +23,10 @@ static struct { u32 cpuid; const char *name; } cpu_table[] = { - { CPUID_ALDERLAKE_A0, "Alderlake Platform" }, - { CPUID_ALDERLAKE_A1, "Alderlake Platform" }, - { CPUID_ALDERLAKE_A2, "Alderlake Platform" }, - { CPUID_ALDERLAKE_A3, "Alderlake Platform" }, + { CPUID_ALDERLAKE_J0, "Alderlake J0 Platform" }, + { CPUID_ALDERLAKE_K0, "Alderlake K0 Platform" }, + { CPUID_ALDERLAKE_Q0, "Alderlake Q0 Platform" }, + { CPUID_ALDERLAKE_R0, "Alderlake R0 Platform" }, { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" }, }; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 2e76cd78c7..fe21b41893 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -273,7 +273,7 @@ static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, const uint32_t cpuid = cpu_get_cpuid(); /* Disable VT-d for early silicon steppings as it results in a CPU hard hang */ - if (cpuid == CPUID_ALDERLAKE_A0 || cpuid == CPUID_ALDERLAKE_A1) { + if (cpuid == CPUID_ALDERLAKE_J0 || cpuid == CPUID_ALDERLAKE_Q0) { m_cfg->VtdDisable = 1; return; } diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 45421c810b..5e79535ecf 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -27,7 +27,7 @@ bool skip_cse_sub_part_update(void) { - return cpu_get_cpuid() != CPUID_ALDERLAKE_A2; + return cpu_get_cpuid() != CPUID_ALDERLAKE_K0; } /* Save the DIMM information for SMBIOS table 17 */ |