diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2022-10-10 10:48:18 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-27 00:34:35 +0000 |
| commit | 9e4488ab06fd9c434a958cfcc5bfd7893a64e1a6 (patch) | |
| tree | 29e4bfe7a442bc8f759e7f57c2682b4e93420607 /src/soc/intel/alderlake | |
| parent | a00db94270f87a82dbe8d83f05f53dbefd0e5a64 (diff) | |
soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS
a) Add LTR disqualification in D3 to ensure PMC ignores LTR
from UFS IP as it is infinite.
b) Remove LTR disqualification in _PS0 to ensure PMC stops
ignoring LTR from UFS IP during D3 exit.
c) Add Kconfig (SOC_INTEL_UFS_LTR_DISQUALIFY) check to apply
this LTR WA.
BUG=b:252975357
TEST=build and boot nirwen and see no issues in PLT runs
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/ufs.h | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index fe7b3a229b..548ef3d712 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -428,6 +428,7 @@ config ACPI_ADL_IPU_ES_SUPPORT config ALDERLAKE_ENABLE_SOC_WORKAROUND bool default y + select SOC_INTEL_UFS_LTR_DISQUALIFY select SOC_INTEL_UFS_OCP_TIMER_DISABLE help Selects the workarounds applicable for Alder Lake SoC. diff --git a/src/soc/intel/alderlake/include/soc/ufs.h b/src/soc/intel/alderlake/include/soc/ufs.h index 3b5e33d0fb..e3a98f2e34 100644 --- a/src/soc/intel/alderlake/include/soc/ufs.h +++ b/src/soc/intel/alderlake/include/soc/ufs.h @@ -22,6 +22,7 @@ #define R_SCS_PCR_5820 0x5820 #define R_SCS_PCR_5C20 0x5C20 #define R_SCS_PCR_1078 0x1078 -#define R_PMC_PWRM_LTR_IGN 0x1B0C +#define R_PMC_PWRM_LTR_IGN 0x1b0c +#define PCH_PWRM_BASE_SIZE 0x1e30 #endif |