diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-01-30 19:09:34 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2023-02-23 08:53:38 +0000 |
| commit | 829e8e65b93963d15367092cd3d364c230465720 (patch) | |
| tree | ebcee8a625ed81f6beffe9a0324c713d6a20b9a6 /src/soc/intel/alderlake | |
| parent | 6b2b8355b321301f39335246afc0db71496961c3 (diff) | |
soc/intel: Use common codeflow for MP init
This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*:
Remove lapic from devicetree).
Alderlake cpu code was linked in romstage but unused so drop it.
Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/cpu.c | 2 |
2 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 2055870251..fa52efbc6f 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -22,7 +22,6 @@ romstage-y += espi.c romstage-y += meminit.c romstage-y += pcie_rp.c romstage-y += reset.c -romstage-y += cpu.c ramstage-y += acpi.c ramstage-y += chip.c diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 27c6a9330d..6b9e5e4ca2 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -188,7 +188,7 @@ static const struct mp_ops mp_ops = { .post_mp_init = post_mp_init, }; -void soc_init_cpus(struct bus *cpu_bus) +void mp_init_cpus(struct bus *cpu_bus) { /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(cpu_bus, &mp_ops); |