soc/intel/{adl, common}: Add routines into CSE IA-common code

This patch adds routines to keep CSE and other HECI devices into the
lower power device state (AKA D0I3).
- cse_set_to_d0i3    =>  Set CSE device state to D0I3
- heci_set_to_d0i3   =>  Function sets D0I3 for all HECI devices

Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI
device count info from SoC layer to common CSE block.

As per PCH EDS, the HECI device count for various SoCs are:

ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4)
APL                     => 1 (CSE)
SKL/Xeon_SP             => 5 (CSE, IDE-R, KT, CSE2 and CSE3)

BUG=b:211954778
TEST=Able to build and boot Brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

1 files changed, 1 insertions, 18 deletions

diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c
index 880e1e02ed..b31395d74a 100644
--- a/src/soc/intel/alderlake/finalize.c
+++ b/src/soc/intel/alderlake/finalize.c
@@ -80,23 +80,6 @@ static void sa_finalize(void)
 		sa_lock_pam();
 }
 
-static void heci_finalize(void)
-{
-	unsigned int cse_dev[] = {
-		PCH_DEVFN_CSE,
-		PCH_DEVFN_CSE_2,
-		PCH_DEVFN_CSE_3,
-		PCH_DEVFN_CSE_4
-	};
-
-	for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) {
-		if (!is_cse_devfn_visible(cse_dev[i]))
-			continue;
-
-		set_cse_device_state(cse_dev[i], DEV_IDLE);
-	}
-}
-
 static void soc_finalize(void *unused)
 {
 	printk(BIOS_DEBUG, "Finalizing chipset.\n");
@@ -105,7 +88,7 @@ static void soc_finalize(void *unused)
 	apm_control(APM_CNT_FINALIZE);
 	tbt_finalize();
 	sa_finalize();
-	heci_finalize();
+	heci_set_to_d0i3();
 	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
 		heci1_disable();