diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-11-08 01:55:12 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-11 11:41:44 +0000 |
| commit | 2dd8f2e13b9e8bf10cd98e707534975f9ebb0ac4 (patch) | |
| tree | 3336f9c2591578282c4a54de4a54795ca1a17a02 /src/soc/intel/alderlake | |
| parent | 03ebbb045f74040b3bd622f537ac01e3663290ca (diff) | |
soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) config
This patch drops the X86_CLFLUSH_CAR config from the latest Intel SoCs
(ADL, MTL, PTL) following the switch to WC (Write-Combining) MTRR type
for the RAMTOP range.
Previously, with WB (Write-Back) caching for RAMTOP, CLFLUSH was
crucial to ensure data consistency, as WB caches both reads and writes.
However, since the RAMTOP range now relies on WC MTRR, the role of
CLFLUSH becomes less critical.
Removing CLFLUSH in this scenario can improve performance, as it avoids
unnecessary cache invalidations.
BUG=b:373290479
TEST=Able to build and boot google/trulo.
Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85028
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index dddf71fe09..f6e918204b 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -96,7 +96,6 @@ config SOC_INTEL_ALDERLAKE select UDK_202111_BINDING if SOC_INTEL_ALDERLAKE_PCH_N select UDK_202005_BINDING if !SOC_INTEL_ALDERLAKE_PCH_N && !SOC_INTEL_RAPTORLAKE select VBOOT_LIB - select X86_CLFLUSH_CAR help Intel Alderlake support. Mainboards should specify the PCH type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead |