diff options
| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-01-30 14:18:21 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-01-31 15:34:13 +0000 |
| commit | 0ad4003cab99a327d5fafa4e43041bc6050fe692 (patch) | |
| tree | 3c5f89e6449b4e4bafd942b7932f12baa58b702b /src/soc/intel/alderlake | |
| parent | 5e5c1daae93c6ab978f8688153fa642365098e56 (diff) | |
soc/intel/alderlake: Pick an unused and safer graphics address space
It turns out that the [0xfa000000-0xfaffffff] range conflicts with
some North TraceHub address space ranges ([0xfad00000-0xfadfffff] and
[0xfacfc000-0xfacfffff]).
Experiments have established that this conflicting range results in an
unpected PIPE A underrun issue reported by i915 and some visible
flickers on the display during boot.
The [0xf0000000-0xffffffff] range is a crowded memory space with
resources statically assigned to some devices but also some ranges
used at various point in the boot flow by the FSP.
To not run into any other potential conflicts, we want to pick a
unused memory space. But at this early stage of the boot, we do not
have full knowledge of what memory space is going to be used by the
FSP. As a result, we decided to pick the [0xaf000000-0xafffffff] range
as:
1. It does not conflicting with any coreboot memory space usage
2. It is the address the FSP uses by default for GFX MMIO BAR0 and as
such should not conflict with any FSP memory space usage.
BUG=b:264648959
BRANCH=firmware-brya-14505.B
TEST=No flickers observed on boot
Change-Id: I6a00350ff4007bb7692d2ff6598b946cc6123302
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72605
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/iomap.h | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 1f0f2feeef..9c5868b0d6 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -208,7 +208,7 @@ config HEAP_SIZE default 0x10000 config GFX_GMA_DEFAULT_MMIO - default 0xfa000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT + default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT # Intel recommends reserving the following resources per PCIe TBT root port, # from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index 94fb5bee09..0c332be2b6 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -88,6 +88,13 @@ #define IOM_BASE_SIZE 0x1600 /* + * If MAINBOARD_HAS_EARLY_LIBGFXINIT is set, the following memory space is used + * at least temporarily in romstage and ramstage as the Intel Graphics Device + * Base Address Range 0. */ +#define IGD_BASE_ADDRESS CONFIG_GFX_GMA_DEFAULT_MMIO +#define IGD_BASE_SIZE 0x1000000 + +/* * I/O port address space */ #define SMBUS_BASE_ADDRESS 0x0efa0 |