diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-06-15 22:44:06 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-17 19:47:11 +0000 |
| commit | 044817762be7fd731ad1688cf5d844958b7067e7 (patch) | |
| tree | 9565e562d021582aec9c191ba0fc5d86082e0ad4 /src/soc/intel/alderlake | |
| parent | b404fa474f9f28d3b8dd7e6aa5671eb05ef26ec8 (diff) | |
soc/intel/{alderlake, common}: Rename the pre_mem_ft structure
The patch renames identifiers (macros, function and structure names) in
the basecode/debug/debug_feature.c to generic names so that they can be
used to control the features which may have to be controlled either
during pre and post memory.
Currently, the naming of identifiers indicate that it meant to control
the features which can be controlled during only pre-memory phase.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I53ceb25454027ab8a5c59400402beb6cc42884c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 48d9a6f64d..31e629ccb5 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -136,7 +136,7 @@ void mainboard_romstage_entry(void) cse_init(HECI1_BASE_ADDRESS); if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) - pre_mem_debug_init(); + dbg_feature_cntrl_init(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; |