soc/intel/adl: Send EOP early in the boot sequence

As part of boot time optimization, one of the culprit was CSE where
response to End Of Post (EOP) command used to take ~60ms. Earlier patch
was pushed to delay the EOP to reduce response time to ~5-7 ms. During
this stage overall platform boot time was ~1.15 seconds.

Once boot time was optimized to ~ 1 seconds, CSE EOP time again
increased to ~80 ms since coreboot used to send EOP at the time where
CSE was busy. This created some back and forth moving of sending EOP
command function within coreboot sequence.
Upon debugging using traces, it was found that coreboot used to send
EOP late where CSE was busy loading other IP payload, so it might take
more time to respond.

In order to avoid delayed response, coreboot has to send EOP in
stage when CSE is done with firmware init and it will be ready to
serve EOP as soon as possible. This also aligns with previous flow where
FSP used to send EOP once silicon init is done and coreboot used to
rely on FSP to send this message.

Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time
reduces from ~60 ms to ~20 ms on Brya board.

Note that once SoC code sends EOP, coreboot common code won't send it
again since common code already has check in case EOP is sent earlier.

BUG=b:211085685
BRANCH=firmware-brya-14505.B
TEST=Tested on Brya system before and after the changes. Observed ~40ms
savings in boot time.

Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>

2 files changed, 16 insertions, 0 deletions

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 0484b17791..38415e695c 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -101,6 +101,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_BASE
 	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_CSE_SEND_EOP_EARLY
 	select SOC_INTEL_CSE_SET_EOP
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index b42322684f..699b39d419 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -6,6 +6,7 @@
 #include <fsp/util.h>
 #include <intelblocks/acpi.h>
 #include <intelblocks/cfg.h>
+#include <intelblocks/cse.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/irq.h>
 #include <intelblocks/itss.h>
@@ -148,6 +149,20 @@ void soc_init_pre_device(void *chip_info)
 
 	/* Swap enabled TBT root ports in device tree if needed. */
 	pcie_rp_update_devicetree(get_tbt_pcie_rp_table());
+
+	/*
+	 * Earlier when coreboot used to send EOP at late as possible caused
+	 * issue of delayed response from CSE since CSE was busy loading payload.
+	 * To resolve the issue, EOP should be sent earlier than current sequence
+	 * in the boot sequence at BS_DEV_INIT.
+	 * Intel CSE team recommends to send EOP close to FW init (between FSP-S exit and
+	 * current boot sequence) to reduce message response time from CSE hence moving
+	 * sending EOP to earlier stage.
+	 */
+	if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY)) {
+		printk(BIOS_INFO, "Sending EOP early from SoC\n");
+		cse_send_end_of_post();
+	}
 }
 
 static void cpu_fill_ssdt(const struct device *dev)