diff options
| author | Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> | 2022-01-16 22:13:14 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-21 15:17:07 +0000 |
| commit | d2ca5be61a9bcf3e246546aa9eaaf87361a0a4ed (patch) | |
| tree | 0745123be63f82e85ff091d38a805aa612444051 /src/soc/intel/alderlake | |
| parent | 8b950f4d7abed355c4d6ee88483a463d20f2da9d (diff) | |
soc/intel/alderlake: Add eMMC ACPI methods for Alder Lake N
Alder Lake N SOC has eMMC device. Add ACPI ASL methods for it.
Change-Id: I53f04e81584493049d37b46e078d394d3c8a2f09
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/acpi/scs.asl | 76 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/acpi/southbridge.asl | 5 |
2 files changed, 81 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/acpi/scs.asl b/src/soc/intel/alderlake/acpi/scs.asl new file mode 100644 index 0000000000..aac78e8fcc --- /dev/null +++ b/src/soc/intel/alderlake/acpi/scs.asl @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pcr_ids.h> + +#define PMCR_D0_MASK 0xFFFC +#define PMCR_D3_MASK 0x0003 + +Scope (\_SB.PCI0) { + + /* + * Clear register 0x1C20/0x4820 + * Arg0 - PCR Port ID + */ + Method(SCSC, 1, Serialized) + { + PCRA (Arg0, 0x1C20, 0x0) + PCRA (Arg0, 0x4820, 0x0) + } + + /* EMMC */ + Device(PEMC) { + Name(_ADR, 0x001A0000) + Name (_DDN, "eMMC Controller") + Name(TEMP, 0) + + OperationRegion(SCSR, PCI_Config, 0x00, 0x100) + Field(SCSR, WordAcc, NoLock, Preserve) { + Offset (0x84), /* PMECTRLSTATUS */ + PMCR, 16, + Offset (0xA2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + Method(_INI) { + /* + * Clear eMMC timeout registers. _PS0 is not called by kernel when + * boot source is not eMMC, but OS still initializes eMMC. So disable + * timeout registers when boot source is not eMMC. Ported from CB:25290. + */ + SCSC (PID_EMMC) + } + + Method(_PS0, 0, Serialized) { + Stall (50) /* Sleep 50 us */ + + PGEN = 0 /* Disable PG */ + + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_EMMC) + + /* Set Power State to D0 */ + PMCR &= PMCR_D0_MASK + /* Additional config read to eMMC controller. Ported from CB:23312 */ + TEMP = PMCR + } + + Method(_PS3, 0, Serialized) { + PGEN = 1 /* Enable PG */ + + /* Set Power State to D3 */ + PMCR |= PMCR_D3_MASK + /* Additional config read to eMMC controller. Ported from CB:23312 */ + TEMP = PMCR + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } + } +} diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 8300c23b7f..3c37d5781b 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -26,6 +26,11 @@ /* Serial IO */ #include "serialio.asl" +/* eMMC */ +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#include "scs.asl" +#endif + /* SMBus 0:1f.4 */ #include <soc/intel/common/block/acpi/acpi/smbus.asl> |