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authorEric Lai <eric_lai@quanta.corp-partner.google.com>2023-06-13 10:21:58 +0800
committerFelix Held <felix-coreboot@felixheld.de>2023-06-15 15:08:12 +0000
commitb15946d72cbf98157ecf5062f5d610f821c0284e (patch)
tree016d0409d4584979802442fc5c24e897377975fc /src/soc/intel/alderlake
parent0acb78b21ff532ebc77b641cb80e5572fc84e0fe (diff)
soc/intel: Add max memory speed into dimm info
Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0. TEST=check dmidecode dump the max speed. Handle 0x000C, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 16 GB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR5 Type Detail: Unknown Synchronous Speed: 5600 MT/s Manufacturer: Micron Serial Number: 3f064d84 Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: MTC8C1084S1SC56BG1 Rank: 1 Configured Memory Speed: 5200 MT/s Minimum Voltage: 1.1 V Maximum Voltage: 1.1 V Configured Voltage: 1.1 V Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75810 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake')
-rw-r--r--src/soc/intel/alderlake/romstage/romstage.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index 740a4a2806..dfe3b323aa 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -140,7 +140,8 @@ static void save_dimm_info(void)
meminfo_hob->EccSupport,
src_dimm->MfgId,
src_dimm->SpdModuleType,
- node);
+ node,
+ meminfo_hob->MaximumMemoryClockSpeed);
index++;
}
}