diff options
| author | Lean Sheng Tan <sheng.tan@9elements.com> | 2022-05-18 17:58:39 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-24 13:05:21 +0000 |
| commit | 79fe6a9537703458ff872e27ab9bc1d19c1380ea (patch) | |
| tree | 77d65fd2e8690184e4ba9d332b2955409f657986 /src/soc/intel/alderlake | |
| parent | 823b7b38e81152735b0f3927e43a88544dbe9c4a (diff) | |
mb/intel/ehlcrb: Adjust TSN GBE settings in devicetree
Set PCH TSN link speed to 1 Gbps and enable MultiVC for all TSN
ports.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I8d43c3ba8f02645c8ad2993f76e610d838b0151a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'src/soc/intel/alderlake')
0 files changed, 0 insertions, 0 deletions