diff options
author | Sean Rhodes <sean@starlabs.systems> | 2023-08-25 13:46:08 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-13 13:13:21 +0000 |
commit | 53048c2a541be7b483d4b916a04c32296e328f41 (patch) | |
tree | 5f49f210f1045ca51fbf4411426196277661c656 /src/soc/intel/alderlake | |
parent | 90e1346d510e7a8b7bd541144c545b7b9bc91b5d (diff) |
soc/intel/{tigerlake,alderlake,meteorlake}: Start to unify the TCSS ACPI
The ACPI used for Tiger Lake, Alder Lake and Meteor Lake are very
similar, so can be moved to shared code.
This commit aligns minor difference between then, such as comments and
tabs/spaces.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If6554c7ef9e83740d7ec5dcca6a9d7e32fb182db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77453
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake')
-rw-r--r-- | src/soc/intel/alderlake/acpi/tcss_dma.asl | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl index ca47bd0ec9..2586ecbbc7 100644 --- a/src/soc/intel/alderlake/acpi/tcss_dma.asl +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -35,6 +35,10 @@ Method (_S0W, 0x0) #endif // D3COLD_SUPPORT } +/* + * Get power resources that are dependent on this device for Operating System Power Management + * to put the device in the D0 device state + */ Method (_PR0) { #if CONFIG(D3COLD_SUPPORT) @@ -49,7 +53,7 @@ Method (_PR0) } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // D3COLD_SUPPORT } Method (_PR3) @@ -74,8 +78,8 @@ Method (_PR3) */ Method (D3CX, 0, Serialized) { - DD3E = 0 /* Disable DMA RTD3 */ - STAT = 0x1 + DD3E = 0x00 /* Disable DMA RTD3 */ + STAT = 0x01 } /* @@ -83,8 +87,8 @@ Method (D3CX, 0, Serialized) */ Method (D3CE, 0, Serialized) { - DD3E = 1 /* Enable DMA RTD3 */ - STAT = 0 + DD3E = 0x01 /* Enable DMA RTD3 */ + STAT = 0x00 } /* |