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authorMichael Niewöhner <foss@mniewoehner.de>2020-10-15 00:36:29 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-10-26 06:51:42 +0000
commita64b4f454894988a9c043d53d00b493852f261a3 (patch)
tree44aacf270999724b4461edb3b4c35959482b4330 /src/soc/intel/alderlake
parentd5a45470c816bc8a8bdc43951c9e4c4a592b55d3 (diff)
mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/soc/intel/alderlake')
-rw-r--r--src/soc/intel/alderlake/chip.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index aaf03f510f..428fd4deeb 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -185,8 +185,6 @@ struct soc_intel_alderlake_config {
uint8_t HeciEnabled;
/* PL2 Override value in Watts */
uint32_t tdp_pl2_override;
- /* Intel Speed Shift Technology */
- uint8_t speed_shift_enable;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
uint8_t eist_enable;