diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2023-05-15 14:35:22 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-26 17:59:15 +0000 |
| commit | e9efd3248550e01a5043860f25239a799d5b19bc (patch) | |
| tree | 1849af0f2edfeb00685ca1ce91eebb238d2b5a40 /src/soc/intel/alderlake/uart.c | |
| parent | 9f15dee56d7fbebe22cb15d55279f05c85a75832 (diff) | |
mb/google/rex: Set frequency and gears for SaGv points
Restrict memory speed to 6400 MTS as per board design.
BUG=b:282164577
TEST=Verified the settings on google/rex using debug FSP logs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3dec383c7c585b80a73089f3403011c5cda61f65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/uart.c')
0 files changed, 0 insertions, 0 deletions