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author | Aamir Bohra <aamir.bohra@intel.com> | 2021-03-02 19:18:30 +0530 |
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committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-03 15:22:14 +0000 |
commit | 1d14ef25f3cb725d682a2fd2738a7002ca9bc23b (patch) | |
tree | 2f7b37232fdbd74143cc4fcbf5f1bcdbd06851be /src/soc/intel/alderlake/spd | |
parent | b77cf2299c516a7f5a9a4eccad2b21157278a283 (diff) |
mb/google/brya: fix BT enumeration issue
Current implementation exposes GPP_F4 cnvi reset pin as reset
gpio instead of GPP_D4(BT_DISABLE_L). GPP_F4 is native and driven
by SoC. It should not be driven by driver.
BUG=b:180875586
Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51178
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/spd')
0 files changed, 0 insertions, 0 deletions