diff options
author | Subrata Banik <subrata.banik@intel.com> | 2020-10-12 17:27:31 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-14 03:39:00 +0000 |
commit | 0aed4e577df03a3c9c790fddebb1a9c413a0abcb (patch) | |
tree | a7300233adea7843f11f4158f0e3c9fcb1e7bb2a /src/soc/intel/alderlake/romstage | |
parent | 8e251f7fceb8df1438be23165bed127fc8b91750 (diff) |
soc/intel/alderlake: Enable TME for Alder Lake
List of changes:
1. Select CONFIG_INTEL_TME from SoC Kconfig
2. Set TmeEnable FSP-M UPD based on Kconfig.
TEST=Able to build and boot ADLRVP and verified from Chrome OS
that TME is enable.
Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46296
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/romstage')
-rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 80420f0948..38c1a1b279 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -155,6 +155,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); + + m_cfg->TmeEnable = CONFIG(INTEL_TME); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |