diff options
| author | Shon Wang <shon.wang@quanta.corp-partner.google.com> | 2021-11-16 11:47:41 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-20 17:48:54 +0000 |
| commit | b39f2a90667a1ac32155a71c43426f383fbe1305 (patch) | |
| tree | 3e040eb2a6e44a0b78f53ea1398a45a759728015 /src/soc/intel/alderlake/reset.c | |
| parent | 1a7afb8363ff58ca0558d005faeb0e45f905d976 (diff) | |
mb/google/brya/var/vell: update memory settings
DQ/DQS info from Intel_Platform_DQ_DQS_RCOMP_Info_Utility
GPIO_MEN_CONFIG_0 GPP_E11 to GPP_E3
GPIO_MEN_CONFIG_3 GPP_E12 to GPP_E7
GPIO_MEM_CH_SEL_GPP_E5 GPP_E13 to GPP_E5
BUG=b:205908918
TEST=emerge-brya coreboot
Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/reset.c')
0 files changed, 0 insertions, 0 deletions