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authorAngel Pons <th3fanbus@gmail.com>2021-02-19 17:49:00 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-24 11:34:42 +0000
commitf5d090d19a695a7ceec83d0b90db7567822a0dce (patch)
tree6ca56a2deba080a33ac12d81adf6963facfc5bcb /src/soc/intel/alderlake/pmutil.c
parenta15a6045d26d10ef095dd26667457e3b2ac3c80b (diff)
soc/intel/*/pmutil.c: Align cosmetics across platforms
Change-Id: I78d1b15deac2b80cc319dcfc5ab6bf419e2d61db Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50931 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/pmutil.c')
-rw-r--r--src/soc/intel/alderlake/pmutil.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c
index 43d5084356..d8308b4019 100644
--- a/src/soc/intel/alderlake/pmutil.c
+++ b/src/soc/intel/alderlake/pmutil.c
@@ -209,10 +209,8 @@ static inline int deep_s3_enabled(void)
}
/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps,
- int prev_sleep_state)
+int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
{
-
/*
* Check for any power failure to determine if this a wake from
* S5 because the PCH does not set the WAK_STS bit when waking