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authorSubrata Banik <subratabanik@google.com>2024-11-16 09:54:14 +0530
committerSubrata Banik <subratabanik@google.com>2024-11-18 02:54:56 +0000
commit640a41f3ee938b794b140218921e0fd63b1d9235 (patch)
tree8731087e83a2c4335b3a6803afec3b1de3935c64 /src/soc/intel/alderlake/pmutil.c
parent3583fe13f7c7914f1a93a71847193862c09782ac (diff)
soc/intel: Assert if `pmc_/gpe0_dwX` values are not unique
This commit adds an assertion to ensure that the values of pmc_/gpe0_dw0, pmc_/gpe0_dw1, and pmc_/gpe0_dw2 in the soc_intel_<soc>_config structure are unique. This check helps to catch potential configuration errors early on, preventing unexpected behavior during system initialization. TEST=Built and booted normally. No assertion failure observed. Able to catch the hidden issue due to overlapping Tier 1 GPE configuration. [DEBUG] CPU: Intel(R) Core(TM) 3 N355 [DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 0000001a [DEBUG] CPU: AES supported, TXT supported, VT supported ... ... [DEBUG] MCH: device id 4617 (rev 00) is Alderlake-N [DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU [DEBUG] IGD: device id 46d3 (rev 00) is Twinlake GT1 [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/pmutil.c', line 163 Change-Id: I6b4f2f90a858b9ec85145bce0542f1ce61d080be Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/pmutil.c')
-rw-r--r--src/soc/intel/alderlake/pmutil.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c
index 050fd5bf88..60d6e10984 100644
--- a/src/soc/intel/alderlake/pmutil.c
+++ b/src/soc/intel/alderlake/pmutil.c
@@ -154,12 +154,23 @@ uint32_t *soc_pmc_etr_addr(void)
return (uint32_t *)(soc_read_pmc_base() + ETR);
}
+static void pmc_gpe0_different_values(const struct soc_intel_alderlake_config *config)
+{
+ bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) &&
+ (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) &&
+ (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2);
+
+ assert(result);
+}
+
void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
{
DEVTREE_CONST struct soc_intel_alderlake_config *config;
config = config_of_soc();
+ pmc_gpe0_different_values(config);
+
/* Assign to out variable */
*dw0 = config->pmc_gpe0_dw0;
*dw1 = config->pmc_gpe0_dw1;