soc/intel/alderlake: Update PCH and CPU PCIe RP table

According ADL EDS to update the PCH and CPU PCIe RP table.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 34 insertions, 0 deletions

diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c
new file mode 100644
index 0000000000..4ec24c265c
--- /dev/null
+++ b/src/soc/intel/alderlake/pcie_rp.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/pcie_rp.h>
+#include <soc/pci_devs.h>
+#include <soc/pcie.h>
+
+static const struct pcie_rp_group pch_lp_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 4 },
+	{ 0 }
+};
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void)
+{
+	return pch_lp_rp_groups;
+}
+
+/*
+ * ADL-P FSP define CPU RP as below:
+ * RP1: PEG60 : 0:6:0 : x4 CPU Slot
+ * RP2: PEG10 : 0:1:0 : x8 CPU Slot
+ * RP3: PEG62 : 0:6:2 : x4 CPU Slot
+ */
+static const struct pcie_rp_group cpu_rp_groups[] = {
+	{ .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1 },
+	{ .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 1 },
+	{ .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1 },
+	{ 0 }
+};
+
+const struct pcie_rp_group *get_cpu_pcie_rp_table(void)
+{
+	return cpu_rp_groups;
+}