diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-11-09 12:13:22 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-11-29 14:39:06 +0000 |
| commit | 95ee5996f70c67c926e907d37f8f1f040fbcb3a6 (patch) | |
| tree | e0b766fb7c4b1e22947faf0086a67218a92f0ef8 /src/soc/intel/alderlake/meminit.c | |
| parent | 3a873b5c9a70ec41488161b491ffe5ac94bb554e (diff) | |
soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration
TEST=Able to pass LPDDR5 MRC training with Lp5CccConfig override.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47436
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/meminit.c')
| -rw-r--r-- | src/soc/intel/alderlake/meminit.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index f5f747d79b..8473ad8a48 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -178,6 +178,7 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg, meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); } + mem_cfg->Lp5CccConfig = board_cfg->lp5_ccc_config; mem_cfg->ECT = board_cfg->ect; mem_cfg->UserBd = board_cfg->UserBd; mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; |