diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-28 13:17:56 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-06-30 08:42:12 +0000 |
| commit | f1f31a38dc44edf0cdab8f19d0cee1a40a426a7d (patch) | |
| tree | 2dbad16a78f450fcf4df6143b532ca62ca8c4f38 /src/soc/intel/alderlake/include | |
| parent | 499b7521d56e85ec9c11fb3d7ea093f107029bdb (diff) | |
soc/intel/alderlake/iomap: Correct the ADL-S reserved range
Due to incorrectly interpreted DOC #630603, the reserved range
remains the same for all ADL platforms and is sync with
src/soc/intel/common/block/acpi/acpi/northbridge.asl which defines the
range as 0xfc800000-0xfe7fffff. The range 0xfe000000-0xfe7fffff was
only mean for static allocations, but the rest is also reserved. The
only difference between ADL-S and other ADL platforms is Trace Hub
base.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I9b1f79cc351de422acf182c27870c29dbe57fe4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/include')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/iomap.h | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index 4f692422db..94fb5bee09 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -13,19 +13,16 @@ * Memory-mapped I/O registers. */ #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) -#define PCH_PRESERVED_BASE_ADDRESS 0xfe000000 -#define PCH_PRESERVED_BASE_SIZE 0x00800000 - #define PCH_TRACE_HUB_BASE_ADDRESS 0xfd800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 #else -#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 -#define PCH_PRESERVED_BASE_SIZE 0x02000000 - #define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 #endif +#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 +#define PCH_PRESERVED_BASE_SIZE 0x02000000 + #define UART_BASE_SIZE 0x1000 #define UART_BASE_0_ADDRESS 0xfe03e000 |