soc/intel/alderlake: Configure the SKU specific parameters for VR domains

This patch configures the SKU specific power delivery parameters for the
VR domains.
+--------------+-------+-------+-------+-------+-----------+--------+
|      SKU     |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time|
|              |       |(mOhms)|(mOhms)|  (A)  |     (A)   |  (msec)|
+--------------+-------+-------+-------+-------+-----------+--------+
|ADL-P 682(45W)|   IA  |  2.3  |  2.3  |  160  |     57    | 28000  |
+              +-------+-------+-------+-------+-----------+--------+
|              |   GT  |  3.2  |  3.2  |   50  |     57    | 28000  |
+--------------+-------+-------+-------+-------+-----------+--------+
|ADL-P 482(28W)|   IA  |  2.3  |  2.3  |  109  |     40    | 28000  |
+              +-------+-------+-------+-------+-----------+--------+
|              |   GT  |  3.2  |  3.2  |   50  |     40    | 28000  |
+--------------+-------+-------+-------+-------+-----------+--------+
|ADL-P 282(15W)|   IA  |  2.8  |  2.8  |   80  |     20    | 28000  |
+              +-------+-------+-------+-------+-----------+--------+
|              |   GT  |  3.2  |  3.2  |   40  |     20    | 28000  |
+--------------+-------+-------+-------+-------+-----------+--------+

These config values are generated iPDG application with ADL-P platform
package tool and supports 15W/28W/45W SKU's.
RDC Kit ID for the iPDG tools,
* Intel(R) Platform Design Studio Installer: 610905.
* Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345.
* Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261.

BUG=b:195033556

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56325
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 71 insertions, 0 deletions

diff --git a/src/soc/intel/alderlake/include/soc/vr_config.h b/src/soc/intel/alderlake/include/soc/vr_config.h
new file mode 100644
index 0000000000..3bf3c4adca
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/vr_config.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* VR Settings for each domain */
+
+#ifndef _SOC_VR_CONFIG_H_
+#define _SOC_VR_CONFIG_H_
+
+#include <fsp/api.h>
+
+struct vr_config {
+
+	/* The below settings will take effect when this is set to 1 for that domain. */
+	bool vr_config_enable;
+
+	/* AC and DC Loadline.
+	   They are in 1/100 mOhms (ie. 1250 = 12.50 mOhms) and range is 0-6249. */
+	uint16_t ac_loadline;
+	uint16_t dc_loadline;
+
+	/* VR Icc Max limit.
+	   Range is from 0-255A in 1/4 A units (400 = 100A). */
+	uint16_t icc_max;
+
+	/* Thermal Design Current time window.
+	   Defined in milli seconds and range 1ms to 448s. */
+	uint32_t tdc_timewindow;
+
+	/* Thermal Design Current current limit.
+	   Defined in 1/8A units and range is 0-4095. 1000 = 125A. */
+	uint16_t tdc_currentlimit;
+};
+
+#define VR_CFG_AMP(i) (uint16_t)((i) * 4)
+#define VR_CFG_MOHMS(i) (uint16_t)((i) * 100)
+#define VR_CFG_TDC_AMP(i) (uint16_t)((i) * 8)
+
+/* VrConfig Settings for 4 domains
+ * 0 = IA core, 1 = GT
+ */
+enum vr_domain {
+	VR_DOMAIN_IA,
+	VR_DOMAIN_GT,
+	NUM_VR_DOMAINS
+};
+
+#define VR_CFG_ALL_DOMAINS_LOADLINE(ia, gt)		\
+	{						\
+		[VR_DOMAIN_IA] = VR_CFG_MOHMS(ia),	\
+		[VR_DOMAIN_GT] = VR_CFG_MOHMS(gt),	\
+	}
+
+#define VR_CFG_ALL_DOMAINS_ICC(ia, gt)			\
+	{						\
+		[VR_DOMAIN_IA] = VR_CFG_AMP(ia),	\
+		[VR_DOMAIN_GT] = VR_CFG_AMP(gt),	\
+	}
+
+#define VR_CFG_ALL_DOMAINS_TDC(ia, gt)	\
+	{				\
+		[VR_DOMAIN_IA] = ia,	\
+		[VR_DOMAIN_GT] = gt,	\
+	}
+
+#define VR_CFG_ALL_DOMAINS_TDC_CURRENT(ia, gt)		\
+	{						\
+		[VR_DOMAIN_IA] = VR_CFG_TDC_AMP(ia),	\
+		[VR_DOMAIN_GT] = VR_CFG_TDC_AMP(gt),	\
+	}
+
+void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, int domain, const struct vr_config *cfg);
+#endif