diff options
| author | Zhuohao Lee <zhuohao@chromium.org> | 2022-01-20 23:36:37 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-02 13:10:21 +0000 |
| commit | b8b40964fc1dae62ab237c1a839b66ec105ad860 (patch) | |
| tree | db18cdf31ca47a97e386010e8339407b0641c589 /src/soc/intel/alderlake/include | |
| parent | 1fcf78cc8eff90881d5d03e38408d584f66a5035 (diff) | |
mb, soc: Add the SPD_CACHE_ENABLE
In order to cache the spd data which reads from the memory module, we
add SPD_CACHE_ENABLE option to enable the cache for the spd data. If
this option is enabled, the RW_SPD_CACHE region needs to be added to
the flash layout for caching the data.
Since the user may remove the memory module after the bios caching the
data, we need to add the invalidate flag to invalidate the mrc cache.
Otherwise, the bios will use the mrc cache and can make the device
malfunction.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and enable this feature to the brask
the device could speed up around 150ms with this feature.
Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/include')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/meminit.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index debdef2ed4..98482e33cc 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -110,6 +110,6 @@ struct mb_cfg { }; void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, - const struct mem_spd *spd_info, bool half_populated); + const struct mem_spd *spd_info, bool half_populated, bool *dimms_changed); #endif /* _SOC_ALDERLAKE_MEMINIT_H_ */ |