diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-02-23 14:03:43 +0530 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-05-10 06:40:37 +0000 |
| commit | 91b2024bae0b35967b07eb30084c3f55fe5aaa4b (patch) | |
| tree | 7631928507b3f2b4f5f780ad7da351de9214399c /src/soc/intel/alderlake/include | |
| parent | 4b97a134857f98c4c0378ab0118b75b5b6a482dc (diff) | |
soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining
We need to modify update CmdMirror and LpDdrDqDqsRetraining parameters
for ADLRVP board.
Allowing this parameters to be filled by devicetree will allow
flexibility to update values as per board designs.
Note that both UPDs are applicable for both DDR and Lpddr memory types.
BUG=None
BRANCH=None
TEST=Build works and UPD values have been filled correctly
Change-Id: I55b4b4aee46231c8c38e208c357b4376ecf6e9d9
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/include')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/meminit.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 96e049cf99..49e3c769bc 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -103,6 +103,12 @@ struct mb_cfg { /* Board type */ uint8_t UserBd; + + /* Command Mirror */ + uint8_t CmdMirror; + + /* Enable/Disable TxDqDqs Retraining for Lp4/Lp5/DDR */ + uint8_t LpDdrDqDqsReTraining; }; void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, |