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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-05-19 09:07:46 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-05-25 12:33:41 +0000
commit827ff248d000afebd4218041284292adf28a55f0 (patch)
treebac10983ff6299f10e4c7fae85a19998b97aa346 /src/soc/intel/alderlake/include
parent6e3f0481117c295ff5722c124b12c88e9bd763e0 (diff)
soc/intel/alderlake: Fix SA_DEVFN_CPU_PCIE6_*
Change-Id: I8849f6dd2a9fdb16642de423cc82dcefd5b192ac Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54682 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/include')
-rw-r--r--src/soc/intel/alderlake/include/soc/pci_devs.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h
index af5c50e70d..f2c2fcb73e 100644
--- a/src/soc/intel/alderlake/include/soc/pci_devs.h
+++ b/src/soc/intel/alderlake/include/soc/pci_devs.h
@@ -41,8 +41,8 @@
#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
#define SA_DEV_SLOT_CPU_6 0x06
-#define SA_DEVFN_CPU_PCIE6_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 0)
-#define SA_DEVFN_CPU_PCIE6_2 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 2)
+#define SA_DEVFN_CPU_PCIE6_0 PCI_DEVFN(SA_DEV_SLOT_CPU_6, 0)
+#define SA_DEVFN_CPU_PCIE6_2 PCI_DEVFN(SA_DEV_SLOT_CPU_6, 2)
#define SA_DEV_SLOT_TBT 0x07
#define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x))