diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-12-31 11:43:29 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:28:51 +0000 |
| commit | f8248f38a10c6dc664b043445233c8f69c3af0f6 (patch) | |
| tree | a2d700007dc43c09fa8878f21750eb39065e3140 /src/soc/intel/alderlake/include | |
| parent | de2ab41fc43152b652af7c1f658b1c27926afd6c (diff) | |
soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/include')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/pci_devs.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/pcie.h | 11 |
2 files changed, 17 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index d86e81ddc2..098c31daa5 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -22,6 +22,9 @@ #define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) #endif +#define SA_DEV_SLOT_CPU_1 0x01 +#define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_1, 0) + #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) @@ -34,8 +37,9 @@ #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) #define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) -#define SA_DEV_SLOT_CPU_PCIE 0x06 -#define SA_DEVFN_CPU_PCIE PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0) +#define SA_DEV_SLOT_CPU_6 0x06 +#define SA_DEVFN_CPU_PCIE6_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 0) +#define SA_DEVFN_CPU_PCIE6_2 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 2) #define SA_DEV_SLOT_TBT 0x07 #define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x)) diff --git a/src/soc/intel/alderlake/include/soc/pcie.h b/src/soc/intel/alderlake/include/soc/pcie.h new file mode 100644 index 0000000000..cd76d09e4a --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pcie.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_ALDERLAKE_PCIE_H__ +#define __SOC_ALDERLAKE_PCIE_H__ + +#include <intelblocks/pcie_rp.h> + +const struct pcie_rp_group *get_pch_pcie_rp_table(void); +const struct pcie_rp_group *get_cpu_pcie_rp_table(void); + +#endif /* __SOC_ALDERLAKE_PCIE_H__ */ |