diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-02-12 09:58:05 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-02-17 22:28:13 +0000 |
| commit | 49889007891de8830428c3092cc6b0977ca165eb (patch) | |
| tree | 2702b0c9cdebc01194cf4b7fcfc70e8b4ed7ae19 /src/soc/intel/alderlake/include | |
| parent | 286c2f6d4a72473b919ea580786d5497f7ef2dec (diff) | |
soc/intel/alderlake: Fix PCI IRQ tables
Both the IO-APIC and PIC mode PCI IRQ tables are incorrect for ADL; the
2nd field in each package is supposed to be pin, not function number,
and some of the IRQ #s differ from what the FSP programs, therefore
align the ACPI table to match what the FSP is currently programming.
BUG=b:180105941
TEST=boot brya, no more `GSI INT` or `failed to derive IRQ routing`
errors seen in dmesg
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I182be69e8d9ebd854ed74dbb69f4d1f1a539cf2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/include')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/irq.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/soc/intel/alderlake/include/soc/irq.h b/src/soc/intel/alderlake/include/soc/irq.h index 98e3f42108..9d471fd90b 100644 --- a/src/soc/intel/alderlake/include/soc/irq.h +++ b/src/soc/intel/alderlake/include/soc/irq.h @@ -17,15 +17,13 @@ #define LPSS_I2C5_IRQ 32 #define LPSS_SPI0_IRQ 36 #define LPSS_SPI1_IRQ 37 -#define LPSS_SPI2_IRQ 34 -#define LPSS_SPI3_IRQ 43 +#define LPSS_SPI2_IRQ 39 #define LPSS_UART0_IRQ 16 #define LPSS_UART1_IRQ 17 #define LPSS_UART2_IRQ 33 +#define LPSS_UART3_IRQ 25 -#define HDA_IRQ 16 -#define SMBUS_IRQ 16 #define TRACEHUB_IRQ 16 #define PCIE_1_IRQ 16 @@ -45,14 +43,14 @@ #define xHCI_IRQ 16 #define xDCI_IRQ 17 -#define CNVI_WIFI_IRQ 16 - -#define CNVI_BT_IRQ 18 #define THC0_IRQ 23 -#define THC1_IRQ 24 +#define THC1_IRQ 22 + +#define ISH_IRQ 26 -#define ISH_IRQ 16 +#define CPU_xHCI_IRQ 16 +#define CPU_xDCI_IRQ 17 #define TBT_PCIe0_IRQ 16 #define TBT_PCIe1_IRQ 17 @@ -61,6 +59,8 @@ #define HECI_1_IRQ 16 #define HECI_2_IRQ 17 +#define CSME_IDE_IRQ 18 +#define CSME_KT_IRQ 19 #define HECI_3_IRQ 16 #define HECI_4_IRQ 19 @@ -69,4 +69,5 @@ #define THERMAL_IRQ 16 #define IPU_IRQ 16 #define GNA_IRQ 16 + #endif |