soc/intel/adl: Add missing claimed memory regions

The Alder Lake chipset has several more reserved memory regions that
are unavailable to the resource allocator than are currently marked
as such in the system agent code. This CL adds the following regions
(documented in Intel docs #626540, #619503):

1. TSEG
2. GSM
3. DSM
4. PCH_RESERVED
5. CRAB_ABORT
6. APIC
7. TPM
8. LT_SECURITY

Claimed regions before this change:
========================================================
base 0        size a0000       // 0 - > 0xa0000
base a0000    size 20000       // legacy VGA
base c0000    size 40000       // RAM
base c0000    size 76f40000    // 0xc0000 -> top_of_ram
base 77000000 size 9400000     // top_of_ram -> TOLUD
base c0000000 size 10000000    // PCIEXBAR
base f8000000 size 2000000     // MMSPI
base fb000000 size 1000        // REGBAR
base fed80000 size 4000        // EDRAMBAR
base fed84000 size 1000        // TBT0BAR
base fed85000 size 1000        // TBT1BAR
base fed86000 size 1000        // TBT2BAR
base fed87000 size 1000        // TBT3BAR
base fed90000 size 1000        // GFXVTBAR
base fed91000 size 1000        // VTVC0BAR
base fed92000 size 1000        // IPUVTBAR
base feda0000 size 1000        // DMIBAR
base feda1000 size 1000        // EPBAR
base fedc0000 size 20000       // MCHBAR
base 100000000 size 17fc00000  // 4GiB -> TOUUD

Claimed regions with this change:
========================================================
base 0        size a0000       // 0 - > 0xa0000
base a0000    size 20000       // legacy VGA
base c0000    size 40000       // RAM
base c0000    size 76f40000    // 0xc0000 -> top_of_ram
base 77000000 size 9400000     // top_of_ram -> TOLUD
base 7b800000 size 800000      // TSEG
base 7c000000 size 800000      // GSM
base 7c800000 size 3c00000     // DSM
base c0000000 size 10000000    // PCIEXBAR
base f8000000 size 2000000     // MMSPI
base fb000000 size 1000        // REGBAR
base fc800000 size 2000000     // PCH_RESERVED
base feb00000 size 80000       // CRAB_ABORT
base fec00000 size 100000      // APIC
base fed40000 size 10000       // TPM
base fed50000 size 20000       // LT_SECURITY
base fed80000 size 4000        // EDRAMBAR
base fed84000 size 1000        // TBT0BAR
base fed85000 size 1000        // TBT1BAR
base fed86000 size 1000        // TBT2BAR
base fed87000 size 1000        // TBT3BAR
base fed90000 size 1000        // GFXVTBAR
base fed91000 size 1000        // VTVC0BAR
base fed92000 size 1000        // IPUVTBAR
base feda0000 size 1000        // DMIBAR
base feda1000 size 1000        // EPBAR
base fedc0000 size 20000       // MCHBAR
base 100000000 size 17fc00000  // 4GiB -> TOUUD

BUG=b:149830546
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage' builds correctly.
Tested on an Anahera device which successfully boots to ChromeOS
with kernel version 5.10.109-15688-g857e654d1705. Also ran dmseg,
and saw the added regions in e820 prints.

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I058a5c1cc59703e35ceddb8a7e26fb22a6a2b75e
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

1 files changed, 26 insertions, 0 deletions

diff --git a/src/soc/intel/alderlake/include/soc/systemagent.h b/src/soc/intel/alderlake/include/soc/systemagent.h
index ebb3d71392..f121b447a7 100644
--- a/src/soc/intel/alderlake/include/soc/systemagent.h
+++ b/src/soc/intel/alderlake/include/soc/systemagent.h
@@ -55,4 +55,30 @@ static const struct sa_mmio_descriptor soc_vtd_resources[] = {
 #define V_P2SB_CFG_HBDF_DEV	30
 #define V_P2SB_CFG_HBDF_FUNC	6
 
+#define CRAB_ABORT_BASE_ADDR	0xFEB00000
+#define CRAB_ABORT_SIZE		(512 * KiB)
+#define TPM_BASE_ADDRESS	0xFED40000
+#define TPM_SIZE		(64 * KiB)
+
+#define LT_SECURITY_BASE_ADDR	0xFED50000
+#define LT_SECURITY_SIZE	(128 * KiB)
+#define APIC_SIZE		(1 * MiB)
+
+#define MASK_PCIEXBAR_LENGTH	0x0000000E // bits [3:1]
+#define PCIEXBAR_LENGTH_LSB	1 // used to shift right
+
+#define DSM_BASE_ADDR_REG	0xB0
+#define  MASK_DSM_LENGTH	0xFF00 // [15:8]
+#define  MASK_DSM_LENGTH_LSB	8 // used to shift right
+#define  MASK_GSM_LENGTH	0xC0 // [7:6]
+#define  MASK_GSM_LENGTH_LSB	6 // used to shift right
+#define DPR_REG			0x5C
+#define  MASK_DPR_LENGTH	0xFF0 // [11:4]
+#define  MASK_DPR_LENGTH_LSB	4 // used to shift right
+
+uint64_t get_mmcfg_size(struct device *dev);
+uint64_t get_dsm_size(struct device *dev);
+uint64_t get_gsm_size(struct device *dev);
+uint64_t get_dpr_size(struct device *dev);
+
 #endif