soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage

List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Add CPU, PCH and SA EDS document number and chapter number
4. Fill required FSP-S UPD to call FSP-S API

Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

12 files changed, 465 insertions, 8 deletions

diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h
new file mode 100644
index 0000000000..3c11183831
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/cpu.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ALDERLAKE_CPU_H_
+#define _SOC_ALDERLAKE_CPU_H_
+
+/* Latency times in us */
+#define C1_LATENCY	1
+#define C6_LATENCY	127
+#define C7_LATENCY	253
+#define C8_LATENCY	260
+#define C9_LATENCY	487
+#define C10_LATENCY	1048
+
+/* Power in units of mW */
+#define C1_POWER	0x3e8
+#define C6_POWER	0x15e
+#define C7_POWER	0xc8
+#define C8_POWER	0xc8
+#define C9_POWER	0xc8
+#define C10_POWER	0xc8
+
+/* Common Timer Copy (CTC) frequency - 38.4MHz. */
+#define CTC_FREQ	38400000
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/irq.h b/src/soc/intel/alderlake/include/soc/irq.h
new file mode 100644
index 0000000000..98e3f42108
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/irq.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_IRQ_H_
+#define _SOC_IRQ_H_
+
+#define GPIO_IRQ14	14
+#define GPIO_IRQ15	15
+
+#define PCH_IRQ10	10
+#define PCH_IRQ11	11
+
+#define LPSS_I2C0_IRQ	27
+#define LPSS_I2C1_IRQ	40
+#define LPSS_I2C2_IRQ	29
+#define LPSS_I2C3_IRQ	30
+#define LPSS_I2C4_IRQ	31
+#define LPSS_I2C5_IRQ	32
+#define LPSS_SPI0_IRQ	36
+#define LPSS_SPI1_IRQ	37
+#define LPSS_SPI2_IRQ	34
+#define LPSS_SPI3_IRQ	43
+
+#define LPSS_UART0_IRQ	16
+#define LPSS_UART1_IRQ	17
+#define LPSS_UART2_IRQ	33
+
+#define HDA_IRQ		16
+#define SMBUS_IRQ	16
+#define TRACEHUB_IRQ	16
+
+#define PCIE_1_IRQ	16
+#define PCIE_2_IRQ	17
+#define PCIE_3_IRQ	18
+#define PCIE_4_IRQ	19
+#define PCIE_5_IRQ	16
+#define PCIE_6_IRQ	17
+#define PCIE_7_IRQ	18
+#define PCIE_8_IRQ	19
+#define PCIE_9_IRQ	16
+#define PCIE_10_IRQ	17
+#define PCIE_11_IRQ	18
+#define PCIE_12_IRQ	19
+
+#define SATA_IRQ	16
+
+#define xHCI_IRQ	16
+#define xDCI_IRQ	17
+#define CNVI_WIFI_IRQ	16
+
+#define CNVI_BT_IRQ	18
+
+#define THC0_IRQ	23
+#define THC1_IRQ	24
+
+#define ISH_IRQ		16
+
+#define TBT_PCIe0_IRQ	16
+#define TBT_PCIe1_IRQ	17
+#define TBT_PCIe2_IRQ	18
+#define TBT_PCIe3_IRQ	19
+
+#define HECI_1_IRQ	16
+#define HECI_2_IRQ	17
+#define HECI_3_IRQ	16
+#define HECI_4_IRQ	19
+
+#define PEG_IRQ		16
+#define IGFX_IRQ	16
+#define THERMAL_IRQ	16
+#define IPU_IRQ		16
+#define GNA_IRQ		16
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/itss.h b/src/soc/intel/alderlake/include/soc/itss.h
new file mode 100644
index 0000000000..ff26c9f97c
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/itss.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_INTEL_ADL_ITSS_H
+#define SOC_INTEL_ADL_ITSS_H
+
+#define GPIO_IRQ_START	50
+#define GPIO_IRQ_END	ITSS_MAX_IRQ
+
+#define ITSS_MAX_IRQ	119
+#define IRQS_PER_IPC	32
+#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
+
+#endif	/* SOC_INTEL_ADL_ITSS_H */
diff --git a/src/soc/intel/alderlake/include/soc/me.h b/src/soc/intel/alderlake/include/soc/me.h
new file mode 100644
index 0000000000..993a3bc29e
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/me.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _ALDERLAKE_ME_H_
+#define _ALDERLAKE_ME_H_
+
+#include <stdint.h>
+
+/* ME Host Firmware Status register 1 */
+union me_hfsts1 {
+	u32 data;
+	struct {
+		u32 working_state: 4;
+		u32 spi_protection_mode: 1;
+		u32 fpt_bad: 1;
+		u32 operation_state: 3;
+		u32 fw_init_complete: 1;
+		u32 ft_bup_ld_flr: 1;
+		u32 update_in_progress: 1;
+		u32 error_code: 4;
+		u32 operation_mode: 4;
+		u32 reset_count: 4;
+		u32 boot_options_present: 1;
+		u32 invoke_enhance_dbg_mode: 1;
+		u32 bist_test_state: 1;
+		u32 bist_reset_request: 1;
+		u32 current_power_source: 2;
+		u32 reserved: 1;
+		u32 d0i3_support_valid: 1;
+	} __packed fields;
+};
+
+/* ME Host Firmware Status Register 3 */
+union me_hfsts3 {
+	u32 data;
+	struct {
+		u32 reserved_0: 4;
+		u32 fw_sku: 3;
+		u32 reserved_7: 2;
+		u32 reserved_9: 2;
+		u32 resered_11: 3;
+		u32 resered_14: 16;
+		u32 reserved_30: 2;
+	} __packed fields;
+};
+#endif /* _ALDERLAKE_ME_H_ */
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h
new file mode 100644
index 0000000000..76930be0e7
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/meminit.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ALDERLAKE_MEMINIT_H_
+#define _SOC_ALDERLAKE_MEMINIT_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fsp/soc_binding.h>
+
+#define BYTES_PER_CHANNEL	2
+#define BITS_PER_BYTE		8
+#define DQS_PER_CHANNEL		2
+
+/* 64-bit Channel identification */
+enum {
+	DDR_CH0,
+	DDR_CH1,
+	DDR_CH2,
+	DDR_CH3,
+	DDR_CH4,
+	DDR_CH5,
+	DDR_CH6,
+	DDR_CH7,
+	DDR_NUM_CHANNELS
+};
+/* Number of memory DIMM slots available on Alderlake board */
+#define NUM_DIMM_SLOT		16
+
+struct spd_by_pointer {
+	size_t spd_data_len;
+	uintptr_t spd_data_ptr;
+};
+
+enum mem_info_read_type {
+	NOT_EXISTING,	/* No memory in this slot */
+	READ_SMBUS,	/* Read on-module spd by SMBUS. */
+	READ_SPD_CBFS,	/* Find SPD file in CBFS. */
+	READ_SPD_MEMPTR	/* Find SPD data from pointer. */
+};
+
+struct spd_info {
+	enum mem_info_read_type read_type;
+	union spd_data_by {
+		/* To read on-module SPD when read_type is READ_SMBUS. */
+		uint8_t spd_smbus_address[NUM_DIMM_SLOT];
+
+		/* To identify SPD file when read_type is READ_SPD_CBFS. */
+		int spd_index;
+
+		/* To find SPD data when read_type is READ_SPD_MEMPTR. */
+		struct spd_by_pointer spd_data_ptr_info;
+	} spd_spec;
+};
+
+/* Board-specific memory configuration information */
+struct mb_cfg {
+	/* DQ mapping */
+	uint8_t dq_map[DDR_NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE];
+
+	/*
+	 * DQS CPU<>DRAM map.  Each array entry represents a
+	 * mapping of a dq bit on the CPU to the bit it's connected to on
+	 * the memory part.  The array index represents the dqs bit number
+	 * on the memory part, and the values in the array represent which
+	 * pin on the CPU that DRAM pin connects to.
+	 */
+	uint8_t dqs_map[DDR_NUM_CHANNELS][DQS_PER_CHANNEL];
+
+	/*
+	 * Rcomp resistor values.  These values represent the resistance in
+	 * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+	 * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+	 */
+	uint16_t rcomp_resistor[3];
+
+	/* Rcomp target values. */
+	uint16_t rcomp_targets[5];
+
+	/*
+	 * Early Command Training Enable/Disable Control
+	 * TRUE = enable, FALSE = disable
+	 */
+	bool ect;
+
+	/* Board type */
+	uint8_t UserBd;
+};
+
+/*
+ * Initialize default memory configurations for Alder Lake.
+ */
+
+void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
+			const struct spd_info *spd_info, bool half_populated);
+
+#endif /* _SOC_ALDERLAKE_MEMINIT_H_ */
diff --git a/src/soc/intel/alderlake/include/soc/nvs.h b/src/soc/intel/alderlake/include/soc/nvs.h
new file mode 100644
index 0000000000..512945898e
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/nvs.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_NVS_H_
+#define _SOC_NVS_H_
+
+#include <intelblocks/nvs.h>
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h
index eedcc27185..d86e81ddc2 100644
--- a/src/soc/intel/alderlake/include/soc/pci_devs.h
+++ b/src/soc/intel/alderlake/include/soc/pci_devs.h
@@ -30,6 +30,10 @@
 #define  SA_DEVFN_DPTF		PCI_DEVFN(SA_DEV_SLOT_DPTF, 0)
 #define  SA_DEV_DPTF		PCI_DEV(0, SA_DEV_SLOT_DPTF, 0)
 
+#define SA_DEV_SLOT_IPU		0x05
+#define  SA_DEVFN_IPU		PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
+#define  SA_DEV_IPU		PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
+
 #define SA_DEV_SLOT_CPU_PCIE	0x06
 #define  SA_DEVFN_CPU_PCIE	PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0)
 
@@ -63,8 +67,10 @@
 #define PCH_DEV_SLOT_SIO0	0x10
 #define  PCH_DEVFN_THC0		_PCH_DEVFN(SIO0, 0)
 #define  PCH_DEVFN_THC1		_PCH_DEVFN(SIO0, 1)
+#define  PCH_DEVFN_CNVI_BT	_PCH_DEVFN(SIO0, 2)
 #define  PCH_DEV_THC0		_PCH_DEV(SIO0, 0)
 #define  PCH_DEV_THC1		_PCH_DEV(SIO0, 1)
+#define  PCH_DEV_CNVI_BT	_PCH_DEV(SIO0, 2)
 
 #define PCH_DEV_SLOT_ISH	0x12
 #define  PCH_DEVFN_ISH		_PCH_DEVFN(ISH, 0)
@@ -72,6 +78,10 @@
 #define  PCH_DEV_ISH		_PCH_DEV(ISH, 0)
 #define  PCH_DEV_GSPI2		_PCH_DEV(ISH, 6)
 
+#define PCH_DEV_SLOT_SIO2	0x13
+#define  PCH_DEVFN_GSPI3	_PCH_DEVFN(SIO2, 0)
+#define  PCH_DEV_GSPI3		_PCH_DEV(SIO2, 0)
+
 #define PCH_DEV_SLOT_XHCI	0x14
 #define  PCH_DEVFN_XHCI		_PCH_DEVFN(XHCI, 0)
 #define  PCH_DEVFN_USBOTG	_PCH_DEVFN(XHCI, 1)
diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h
index 03fe02fee1..e4e3dfb690 100644
--- a/src/soc/intel/alderlake/include/soc/pmc.h
+++ b/src/soc/intel/alderlake/include/soc/pmc.h
@@ -2,6 +2,9 @@
 
 #ifndef _SOC_ALDERLAKE_PMC_H_
 #define _SOC_ALDERLAKE_PMC_H_
+#include <device/device.h>
+
+extern struct device_operations pmc_ops;
 
 /* PCI Configuration Space (D31:F2): PMC */
 #define  PWRMBASE		0x10
diff --git a/src/soc/intel/alderlake/include/soc/ramstage.h b/src/soc/intel/alderlake/include/soc/ramstage.h
new file mode 100644
index 0000000000..e655198316
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/ramstage.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <soc/soc_chip.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config);
+void soc_init_pre_device(void *chip_info);
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/serialio.h b/src/soc/intel/alderlake/include/soc/serialio.h
new file mode 100644
index 0000000000..e42af5f781
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/serialio.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SERIALIO_H_
+#define _SERIALIO_H_
+
+enum {
+	PchSerialIoDisabled,
+	PchSerialIoPci,
+	PchSerialIoHidden,
+	PchSerialIoLegacyUart,
+	PchSerialIoSkipInit
+};
+
+enum {
+	PchSerialIoIndexI2C0,
+	PchSerialIoIndexI2C1,
+	PchSerialIoIndexI2C2,
+	PchSerialIoIndexI2C3,
+	PchSerialIoIndexI2C4,
+	PchSerialIoIndexI2C5,
+};
+
+enum {
+	PchSerialIoIndexGSPI0,
+	PchSerialIoIndexGSPI1,
+	PchSerialIoIndexGSPI2,
+	PchSerialIoIndexGSPI3,
+};
+
+enum {
+	PchSerialIoIndexUART0,
+	PchSerialIoIndexUART1,
+	PchSerialIoIndexUART2,
+};
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/systemagent.h b/src/soc/intel/alderlake/include/soc/systemagent.h
index b564e7d07f..ebb3d71392 100644
--- a/src/soc/intel/alderlake/include/soc/systemagent.h
+++ b/src/soc/intel/alderlake/include/soc/systemagent.h
@@ -31,10 +31,7 @@
 #define IMRBASE			0x6a40
 #define IMRLIMIT		0x6a48
 #define IPUVTBAR		0x7880
-#define TBT0BAR			0x7888
-#define TBT1BAR			0x7890
-#define TBT2BAR			0x7898
-#define TBT3BAR			0x78a0
+#define TBTxBAR(x)		(0x7888 + (x) * 8)
 
 #define MAX_TBT_PCIE_PORT	4
 
@@ -44,10 +41,10 @@
 static const struct sa_mmio_descriptor soc_vtd_resources[] = {
 	{ GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
 	{ IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" },
-	{ TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" },
-	{ TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" },
-	{ TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" },
-	{ TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" },
+	{ TBTxBAR(0), TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" },
+	{ TBTxBAR(1), TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" },
+	{ TBTxBAR(2), TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" },
+	{ TBTxBAR(3), TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" },
 	{ VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
 };
 
diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h
new file mode 100644
index 0000000000..846849aa60
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/usb.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_USB_H_
+#define _SOC_USB_H_
+
+#include <stdint.h>
+
+/* Per Port HS Transmitter Emphasis */
+#define USB2_EMP_OFF			0
+#define USB2_DE_EMP_ON			1
+#define USB2_PRE_EMP_ON			2
+#define USB2_DE_EMP_ON_PRE_EMP_ON	3
+
+/* Per Port Half Bit Pre-emphasis */
+#define USB2_FULL_BIT_PRE_EMP	0
+#define USB2_HALF_BIT_PRE_EMP	1
+
+/* Per Port HS Preemphasis Bias */
+#define USB2_BIAS_0MV		0
+#define USB2_BIAS_11P25MV	1
+#define USB2_BIAS_16P9MV	2
+#define USB2_BIAS_28P15MV	3
+#define USB2_BIAS_39P35MV	5
+#define USB2_BIAS_45MV		6
+#define USB2_BIAS_56P3MV	7
+
+struct usb2_port_config {
+	uint8_t enable;
+	uint8_t ocpin;
+	uint8_t tx_bias;
+	uint8_t tx_emp_enable;
+	uint8_t pre_emp_bias;
+	uint8_t pre_emp_bit;
+};
+
+/* USB Overcurrent pins definition */
+enum {
+	OC0 = 0,
+	OC1,
+	OC2,
+	OC3,
+	OC4,
+	OC5,
+	OC6,
+	OC7,
+	OCMAX,
+	OC_SKIP = 0xff, /* Skip OC programming */
+};
+
+/* Standard USB Port based on length:
+ * - External
+ * - Back Panel
+ * - OTG
+ * - M.2
+ * - Internal device down */
+
+#define USB2_PORT_EMPTY { \
+	.enable        = 0, \
+	.ocpin         = OC_SKIP, \
+	.tx_bias       = USB2_BIAS_0MV, \
+	.tx_emp_enable = USB2_EMP_OFF, \
+	.pre_emp_bias  = USB2_BIAS_0MV, \
+	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Length = 11.5"-12" */
+#define USB2_PORT_LONG(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_39P35MV, \
+	.tx_emp_enable = USB2_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_56P3MV, \
+	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Length  = 6"-11.49" */
+#define USB2_PORT_MID(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_0MV, \
+	.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_45MV, \
+	.pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
+}
+
+/* Length = 3"-5.99" */
+#define USB2_PORT_SHORT(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_39P35MV, \
+	.tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_39P35MV, \
+	.pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
+}
+
+/* Max TX and Pre-emp settings */
+#define USB2_PORT_MAX(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_56P3MV, \
+	.tx_emp_enable = USB2_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_56P3MV, \
+	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Type-C Port, no BC1.2 charge detect module / MUX
+ * Length  = 3.0" - 9.00" */
+#define USB2_PORT_TYPE_C(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_0MV, \
+	.tx_emp_enable = USB2_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_56P3MV, \
+	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+}
+
+struct usb3_port_config {
+	uint8_t enable;
+	uint8_t ocpin;
+	uint8_t tx_de_emp;
+	uint8_t tx_downscale_amp;
+};
+
+#define USB3_PORT_EMPTY { \
+	.enable           = 0, \
+	.ocpin            = OC_SKIP, \
+	.tx_de_emp        = 0x00, \
+	.tx_downscale_amp = 0x00, \
+}
+
+#define USB3_PORT_DEFAULT(pin) { \
+	.enable           = 1, \
+	.ocpin            = (pin), \
+	.tx_de_emp        = 0x0, \
+	.tx_downscale_amp = 0x00, \
+}
+
+#endif