diff options
| author | Cliff Huang <cliff.huang@intel.com> | 2024-08-19 10:03:10 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-22 13:25:40 +0000 |
| commit | 1c6548d5ccfcc550b209ac9cef401883ffdc34ff (patch) | |
| tree | c005a0e4fd72b5de785306f1e16493e81d8dcf25 /src/soc/intel/alderlake/include | |
| parent | 2d4afd8fd99b46e9f1971ef9156d4cb72a53eddf (diff) | |
soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdr
These field defines are SOC-specific. The AUX bias virtual wire field
positons are shifted in PTL.
In MTL SOC and older:
7:0 GROUP_ID Group ID in PCH GPIO
10:8 BIT_NUM Data bit Position in PCH GPIO
23:16 VW_INDEX VW Index in PCH GPIO
In PTL SOC:
15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID
18:16 BIT_NUM Data bit Position in PCH GPIO
31:24 VW_INDEX VW Index in PCH GPIO
BUG=361048817
TEST=boot to OS and use iotools to read AUX Bias Ctrl register to
verify the group ID, bit number, and vw index.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83980
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Diffstat (limited to 'src/soc/intel/alderlake/include')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/tcss.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/tcss.h b/src/soc/intel/alderlake/include/soc/tcss.h index 825b6c78b9..079d3bc833 100644 --- a/src/soc/intel/alderlake/include/soc/tcss.h +++ b/src/soc/intel/alderlake/include/soc/tcss.h @@ -17,4 +17,7 @@ #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088 #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4) +#define BIAS_CTRL_VW_INDEX_SHIFT 16 +#define BIAS_CTRL_BIT_POS_SHIFT 8 + #endif /* _SOC_TCSS_H_ */ |