diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-11-09 12:13:22 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-11-29 14:39:06 +0000 |
| commit | 95ee5996f70c67c926e907d37f8f1f040fbcb3a6 (patch) | |
| tree | e0b766fb7c4b1e22947faf0086a67218a92f0ef8 /src/soc/intel/alderlake/include | |
| parent | 3a873b5c9a70ec41488161b491ffe5ac94bb554e (diff) | |
soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration
TEST=Able to pass LPDDR5 MRC training with Lp5CccConfig override.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47436
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/include')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/meminit.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 5fed5680c6..36d0750d37 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -90,6 +90,14 @@ struct mb_cfg { /* Board type */ uint8_t UserBd; + + /* + * Command pins mapping for Controller Channel (ccc) + * lp5_ccc_config: Bitmask where bits [3:0] are Controller 0 Channel [3:0] and + * bits [7:4] are Controller 1 Channel [3:0] + * Bit value: 0 = ccc pin mapping is ascending, 1 = ccc pin mapping is descending. + */ + uint8_t lp5_ccc_config; }; /* |