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| author | Subrata Banik <subratabanik@google.com> | 2024-09-15 10:50:19 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-17 04:38:00 +0000 |
| commit | b9a09786bcc7f98735d23a58a9119cb4a744b923 (patch) | |
| tree | f97fba1269f1548a3153691fcb5eaf96b3c82197 /src/soc/intel/alderlake/i2c.c | |
| parent | 285b74ab26caf4e62cd37c376f13256c68cd4ce7 (diff) | |
Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"
This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309.
This workaround is not valid with the latest Intel PRQ silicon,
so I'm dropping it now. Additionally, able to boot to ChromeOS without
any hang, and I also ran an S0ix cycle without any failures.
BUG=b:244082753
TEST=Able to boot google/rex0 to CrOS.
Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84368
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/i2c.c')
0 files changed, 0 insertions, 0 deletions